QtRvSim: all versions and old releases

- Machine/GUI: Not Most Recently Used cache policy by brsf11
- Machine/GUI: lot of speedup optimizations by Jakub Dupak
- Core: use QElapsedTimer for similar speedup by Jakub Dupak
- GUI: Show core frequency by Jakub Dupak
- Packaging: updated SUSE packaging based on consultation with Lubos Kocman
- Assembler: correct %hi operator result for lower 12 bits values above 0x7ff
- Predictor: always taken result fix by Stepan Pressl
- Project: add riscv nix shells
- GUI: Ignore updates on hidden registers and batch update when shown
- GUI: Performance optimizations by Jakub Dupak
- CLI: defer start of code (play) to be run from QCoreApplication main event loop
- CLI: Implemented console option to dump the symbol table by Markus Gschoßmann
- Project: replace libelf with libelfin by Jakub Dupak
- GUI: fix zoom scaling issue by Adam Nemec
- Machine: add supervisor CSRs and sstatus handling by Adam Nemec
- Machine: add TLB with policies and add Sv32 by Adam Nemec
- GUI: add TLB visualization and statistics dock by Adam Nemec
- GUI: add "As CPU (VMA)" memory access view by Adam Nemec
- Sv32 MMU Implementation by Adam Nemec
- Branch predictor and L2 cache access cli configuratio by Thanasis Kyprianos
- Docs: Initial version of the User Manual in simple MarkDown format by Filip Kraus
- CI: Deploy user manual as github pages by Jakub Dupak
- GUI: use AddressWithMode to prevent crashes in memory view
- CLI: Add support for mapping stdin to a host file in syscall emulation by Naoya Niwa
- Machine: add SV39 / 64-bit page-table walker and TLB support by Adam Nemec
- Support for xv6 (MIT PDOS), S-mode CSR and more by Adam Nemec
- Docs: add virtual memory (TLB) documentation by Adam Nemec
- GUI: Separate GUI into a library by Jakub Dupak
- Project: switch libelfin to cvut fork by Jakub Dupak
- Machine: work on MMU, TLB, memory and modes logic to really work by Pavel Pisa
- Machine: extend memory-backed to support large/64-bit memory
- GUI: program view read and write access through TLB and cache synchronization
- Machine: add Sv39 support of PBMT, uncached control by page table
- feat: added webeval integration to submit and load tasks by Jakub Pelc
- Machine: postpone CSR access fault to commit stage
- GUI: adapt address HexLineEdit and address column in memory views to XLEN64
- Machine: use CachePolicy for replacement computations in TLB
- Machine: implement read and write access modifications by mstatus.MPRV
- Packaging: switch to Qt6 as default, keep Qt5 for old distributions
- Machine: set UXL in sstatus to 2 for RV64 ISA variant
- CI: Use temporary GitHub mirror for stud-support tests (stopgap)
- Debuginfo integration to integrated assembler and ELF up-to Dwarf-4 by Jakub Dupak
- Project: move generated project_info.h to the project build directory
- GUI: fix "#pragma qtrvsim tab core" function
- GUI: delay printer and print dialog initialization by Jakub Dupak
- Machine: Deliver exception cause as argument to stop_on_exception_reached()
- example: page-to-page-copy.S example to demostrate MMU function added by Petr Stepan
For Ubuntu use https://launchpad.net/~qtrvsimteam/+archive/ubuntu/ppa
For SUSE, Fedora and Debian https://software.opensuse.org/download.html?project=home%3Ajdupak&package=qtrvsim
For Arch https://aur.archlinux.org/pkgbase/qtrvsim
WebAssembly online version https://comparch.edu.cvut.cz/qtrvsim/app
QtRvSim articles, presentations, and their recordings, as well as more about Computer Architectures courses at the Czech Technical University in Prague, are presented at https://comparch.edu.cvut.cz/
The educational VHDL RISC-V core modeled according to the QtRvSim (single-cycle and 5-stage pipeline) has been designed by Damir Gruncl for the CTU FEE Advanced Computer Architectures course (RVapo VHDL sources and tested in GHDL simulations, on Xilinx Zynq and iCE-40 FPGA targets. On the Zynq target, it runs as a PMSM motor control coprocessor to perform inverse and forward Clarke and Park transformations and other low-level contro

- Machine: aclintmtimer fix count type
- GUI: fix a crash on nonexistent include
- Use win32 config of libelf when compiling natively for Windows
- CI: Add Windows Clang debug build and macos ARM
- CLI: reporter dump to json
- Machine: instruction parsing refactor
- GUI: make printer settings persistent and scale to fit PDF page size
- Assembler: fix immediate parsing
- Assembler: implement GAS modifiers - PC rel still basic only
- Machine: fix zext.w/h inst parse and fix tokenized for inst.xxx
- Machine: fix parse_csr_address and CSR::RegisterMapByName key type
- Machine and GUI: Pseudo LRU cache policy
- Add 25x speed for teaching convenience
- Machien and GUI: Include Jiri Stefan's work on branch predictor
- Machien and GUI: BTB, BHT and BHR are implemented
- Project: Explicit cmake qt major version option
- Packaging: add Keywords entry into desktop file
- Machine: add peripherals high/top address aliases for XLEN=64
- GUI: switch "New" dialog page selection to tree widget, polishing required

For Ubuntu use https://launchpad.net/~qtrvsimteam/+archive/ubuntu/ppa
For SUSE, Fedora and Debian https://software.opensuse.org/download.html?project=home%3Ajdupak&package=qtrvsim
For Arch https://aur.archlinux.org/pkgbase/qtrvsim
WebAssembly online version https://comparch.edu.cvut.cz/qtrvsim/app

QtRvSim articles, presentations and their recordings as well as more about Computer Architectures
courses at the Czech Technical University in Prague are presented at https://comparch.edu.cvut.cz/

The educational VHDL RISC-V core modeled according to the QtRvSim (single cycle and 5-stage
pipeline) has been designed by Damir Gruncl for the CTU FEE Advanced Computer Architectures course
(RVapo VHDL sources and tested in GHDL simulation, on Xilinx Zynq and iCE-40 FPGA targets. On Zynq
target it runs as PMSM motor control coprocessor to solve inverse and forward Clarke and Park
transformations and other low level control (top level project). See the complete list of the OTREES
CTU theses for more related topics.

The online training site for QtRvSim processed assembly and C tasks evaluation has been prepared by
Jakub Pelc https://comparch.edu.cvut.cz/online-tools/webeval/

QtRvSim news and the evaluation web will be presented on RISC-V International Special Interest
Group: Academia and Training meeting at October 10 2024 at 8 AM Pacific Time (5 PM CEST). The
feedback is welcomed. I will be present on 2024 RISC-V Summit North America (October 22-23, 2024) as
well. I will be happy to see you there and discuss teaching, Linux, RTEMS, NuttX real time topics
and development, motion control and robotics.