QtRvSim: παλαιότερες εκδόσεις και ιστορικό

- Machine: aclintmtimer fix count type
- GUI: fix a crash on nonexistent include
- Use win32 config of libelf when compiling natively for Windows
- CI: Add Windows Clang debug build and macos ARM
- CLI: reporter dump to json
- Machine: instruction parsing refactor
- GUI: make printer settings persistent and scale to fit PDF page size
- Assembler: fix immediate parsing
- Assembler: implement GAS modifiers - PC rel still basic only
- Machine: fix zext.w/h inst parse and fix tokenized for inst.xxx
- Machine: fix parse_csr_address and CSR::RegisterMapByName key type
- Machine and GUI: Pseudo LRU cache policy
- Add 25x speed for teaching convenience
- Machien and GUI: Include Jiri Stefan's work on branch predictor
- Machien and GUI: BTB, BHT and BHR are implemented
- Project: Explicit cmake qt major version option
- Packaging: add Keywords entry into desktop file
- Machine: add peripherals high/top address aliases for XLEN=64
- GUI: switch "New" dialog page selection to tree widget, polishing required

For Ubuntu use https://launchpad.net/~qtrvsimteam/+archive/ubuntu/ppa
For SUSE, Fedora and Debian https://software.opensuse.org/download.html?project=home%3Ajdupak&package=qtrvsim
For Arch https://aur.archlinux.org/pkgbase/qtrvsim
WebAssembly online version https://comparch.edu.cvut.cz/qtrvsim/app

QtRvSim articles, presentations and their recordings as well as more about Computer Architectures
courses at the Czech Technical University in Prague are presented at https://comparch.edu.cvut.cz/

The educational VHDL RISC-V core modeled according to the QtRvSim (single cycle and 5-stage
pipeline) has been designed by Damir Gruncl for the CTU FEE Advanced Computer Architectures course
(RVapo VHDL sources and tested in GHDL simulation, on Xilinx Zynq and iCE-40 FPGA targets. On Zynq
target it runs as PMSM motor control coprocessor to solve inverse and forward Clarke and Park
transformations and other low level control (top level project). See the complete list of the OTREES
CTU theses for more related topics.

The online training site for QtRvSim processed assembly and C tasks evaluation has been prepared by
Jakub Pelc https://comparch.edu.cvut.cz/online-tools/webeval/

QtRvSim news and the evaluation web will be presented on RISC-V International Special Interest
Group: Academia and Training meeting at October 10 2024 at 8 AM Pacific Time (5 PM CEST). The
feedback is welcomed. I will be present on 2024 RISC-V Summit North America (October 22-23, 2024) as
well. I will be happy to see you there and discuss teaching, Linux, RTEMS, NuttX real time topics
and development, motion control and robotics.