Logisim-evolution 이전 버전 및 전체 버전

- v5.0.0 (2026-09-12)
- Added Find Action omni-search with fuzzy and acronym matching.
- Added image component support for custom bitmap images in circuits and subcircuit appearances.
- Added new components including Real-Time Clock, Floating Point Constant, and multiple TTL devices.
- Improved dark theme color synchronization across canvas, components, icons, and wires.
- Improved timing diagram recording/exports and custom circuit appearance editing behavior.
- Improved memory/hex editor tools, including go-to-address and clearer RAM behavior labels.
- Improved project editing stability, view persistence, and text-editing undo/redo behavior.
- Improved command-line behavior and localization, including nonzero exit on invalid options.
- Fixed Java accessibility runtime launch failures and various HDL/FPGA generation issues.
- Many other bug fixes and documentation updates.

- v4.1.0 (2026-02-15)
- Increased number of components which may be displayed on custom circuit appearances and increased
options for existing ones.
- Bug fixes:
- Fixed more synchronization issues with simulation tree and propagator.
- Fixed INOUT port issue in TTL74245.
- Fixed several other minor issues.
- Enhanced TestVector for sequential circuits. See user's guide for details.
- Enhanced Video resolution choices.
- Allow more components to show in State (register) tab.
- Enhanced Undo and Redo functionality:
- Added "Undo History" dropdown menu to view and select specific undo actions.
- Added "Redo History" dropdown menu to view and select specific redo actions.
- Added "Clear Undo/Redo History" menu item with confirmation dialog.
- Limited undo and redo history to a maximum of 64 actions.
- Retained standard single-step undo and redo functionality via menu item.
- Enhanced Counter component:
- Counter state can now be displayed in "State" tab alongside registers.
- Counter state can now drive "Assembly viewer" address.
- Corrected appearance of OR gates in TikZ/SVG image exports.
- Corrected font choice for default fonts in SVG image exports.
- Reduced filesize of TikZ/SVG image exports.
- Enhanced SoC component labels.
- Enhanced Chinese localization.
- Added DMA copy engine component (SocDma) in the System On Chip library.

- v4.0.0 (2025-09-07)
- Updated VHDL and created Verilog generator for RAM component with byte-enables
- Added VHDL and Verilog for the RAM component with line-enables
- fixed clasic appearance shift-register bug
- Added automatic custom Logisim library loading at startup.
- Created unit tests for loading custom Logisim libraries at startup.
- Updated documentation for the automatic loading of custom Logisim libraries.
- New take on project export/import. A zip-file is generated which can include a user provided "README.md".
- Added Telnet component.
- Added Metal graphics acceleration option.
- Added option to hide/show toolbar
- Improved drawing appearance.
- Fixed TTY appearance bug while changing various zoom levels.
- Corrected appearance of NOT gates in TikZ/SVG image export.
- Corrected disjoint corners in arrow-style Pins.
- Improved output of rectangles with rounded corners in TikZ image export.
- Fixed Undo/Redo issues.
- Fixed Power-on-Reset propagation issue.
- Redesigned simulation engine to fix synchronization issues and increase speed.
- Fixed synchronization and efficiency issues in wires and propagation.
- Fixed synchronization and efficiency issues in propagation listeners.
- Limited redraws to about 20 frames per second to reduce overhead.
- Allows users to choose a simulation queue, which changes the efficiency of the simulator depending on circuit design.
- Simplified Type and Behavior attributes of Pins.
- This change will break circuits with input pins that need to pull floating values to 0 but do not
have the Pull Down setting. To fix it, set the Behavior attribute to Pull Down.
- Updated Pin documentation.
- Subcircuits with clock input(s) are now drawn with a clock symbol.
- Added TTL 74194: 4-bit bidirectional universal shift register.
- Improved the English, French, and German localization. Smaller fixes were done to the other languages as well.

- Updated Java requirement to Java 21.
- Added an autosave feature along with preferences for it.
- Added a new preference to allow the user to choose the action keys for many functions.
- Changed RAM default output from error to undefined [#1747]
- Added support for scanning 7-segment display on FPGA-boards
- Added first support for the openFpga toolchain for the ecp5 famely
Note that this is experimental for the moment, so use it at your own risk.
- Improved Chinese localization
- Changed language code from cn to zh.
- Chinese users (also including those who use other forks of Logisim
that are using cn language code) will be required to manually modify language settings.
- Fixed select port positioning on Multiplexer to be more consistent in some cases [#1734]
- Fixed appearance of LSe desktop icon [#1662]
- Update controlled buffer behavior to pass U and E inputs while enabled [#1642]
- Introduced user-defined color for components.
- Made component icons more uniform.
- Added architecture designation to macOS build.
- Fixed Karnaugh map color index bug.
- Attribute sheet now honors application color theme.
- Attribute sheet now displays HEX value of color properties.
- Added TTL 7487: 4-bit True/complement, zero/one elements
- Fixed Wrong HDL generation bug in the PortIO component and added the single bit version.
- Added TTL 74151: 8-line to 1 line data selector
- Added TTL 74153: dual 4-line to 1 line data selector
- Added TTL 74181: arithmetic logic unit
- Added TTL 74182: look-ahead carry generator
- Added TTL 74299: 8-bit universal shift register with three-state outputs
- Added TTL 74381: arithmetic logic unit
- Added TTL 74541: Octal buffers with three-state outputs
- Added TTL 74670: 4-by-4 register file with three-state outputs
- Added 16 bit floating point support for floating point arithmetic
- Fixed the problem of keys getting assigned to focusing on the cell of the table in "properties" section along with its actual intent